Digital serial transmission is widely used in many fields and devices, such as in the communication network system or for PCI Express, Serial ATA (SATA), and the like in a personal computer. In the communication system, for example, the International Telecommunication Union (ITU) defines standards for various data rates from a low speed (1.5 Mbps) to a high speed (10 Gbps) as Synchronous Digital Hierarchy (SDH). SDH transmission equipment is often required to support many data rates, instead of a single data rate, by changing the setting thereof. For example, there are cases where equipment including a Synchronous Transfer Mode (STM), which is an optical transmission system, needs to support data rates such as STM1 (155.52 Mbps), STM4 (622.08 Mbps), and STM16 (2.48832 Gbps) by changing the setting thereof.
In digital serial transmission, a clock data recovery circuit is used. Based on the circuit, while clock signals are not transmitted, data signals are transmitted. When receiving data, the receiving end reproduces a clock synchronized with the data. As an example of such clock data recovery circuit, Patent Document 1 discloses a clock and data recovery circuit using multiphase clocks. This circuit comprises a phase-shift circuit for shifting phases of the multiphase clocks and outputting the resultant clock signals. According to this document, input data is latched by multiphase clocks outputted from the phase-shift circuit, and based on the latched data, the relationship between a phase of data transition and phases of the multiphase clocks is detected. By controlling the phase-shift circuit based on the relationship so that the phases of the multiphase clocks follow the data transition, a clock synchronized with the input data is reproduced.
Patent Document 1: Japanese Patent Kokai Publication No. JP-P2003-333021A